Vertical transistors are conventionally used as semiconductor devices which are able to be miniaturized. In a vertical transistor, a gate insulating film and a gate electrode are provided on the side surface of a semiconductor pillar extending perpendicularly from the main surface of a semiconductor substrate, and a source and drain are provided above and below the pillar.
A vertical transistor makes it possible to achieve a fully depleted semiconductor device by narrowing the pillar diameter to a certain extent. In a fully depleted semiconductor device, the S coefficient is small and variations in the threshold voltage Vt can be reduced. As a result, it is possible to achieve a low-voltage/high-performance semiconductor device. Furthermore, it is possible to reduce the area occupied because of a two-dimensional structure, and this is also very advantageous for making the device more compact.
Patent Document 1 (JP 2012-89772 A) describes a semiconductor device employing a vertical transistor. In that semiconductor device, a dummy pillar is provided in the vicinity of a semiconductor pillar, and a gate electrode is provided continuously on the side surfaces of the semiconductor pillar and the dummy pillar. Furthermore, a gate contact is formed on the gate electrode on the side surface of the dummy pillar.